1. Field
Exemplary embodiments of the present invention relate to a memory device, and more particularly, to a technology for improving the bandwidth of a memory device.
2. Description of the Related Art
Recently, both the capacity and speed of a semiconductor memory used as a storage device in most of electronic systems have tended to increase. Furthermore, various attempts are being made to mount memory having a higher capacity within a narrower area and to efficiently drive memory.
Furthermore, to improve the degree of integration of pieces of memory, a three-dimensional (3D) stack technology in which a plurality of memory chips are stacked, is being applied instead of an existing two-dimensional (2D) arrangement. In accordance with the requirements of higher-integration and higher-capacity memory, a structure for improving the degree of integration by reducing the size of a semiconductor chip using the 3D stack structure of memory chips as well as increasing the capacity has been developed.
FIG. 1 is a diagram illustrating the configuration of conventional memory device.
Referring to FIG. 1, the memory device 100 may include a plurality of multi-channel memories 120_1 and 120_2 and an interface unit 110.
The multi-channel memories 120_1 and 120_2 can support a multi-channel operation. A first channel CH1 and a second channel CH2 have independent command buses, address buses, and data buses and may operate independently. FIG. 1 represents the command bus, address bus, and data bus of the first and second channels CH1 and CH2 with respective single lines.
The interface unit 110 may function as an interface between the multi-channel memories 120_1 and 120_2 and a device outside the memory device such as, a memory controller or a GPU and CPU including a memory controller.